LSI Corporation Hiring Fresh Engineers (LSI Careers)
About us: LSI Corporation designs, develops, and markets storage and networking semiconductors worldwide. Its storage product portfolio includes hard disk, solid state, and tape drive solutions, which enable the reading and writing of digital data to and from the storage media, such as the hard disk drive platter or the flash memory cell; server and storage connectivity solutions, which facilitate secured data transfers between host systems, such as servers and storage devices; and custom storage solutions that enable high speed storage data communication between servers and external storage systems over a switched storage network, such as a fiber channel storage area network. The company's networking portfolio comprises solutions for multi-service wired and wireless access systems found in carrier networks, as well as solutions typically used in small office, home office, and small-to-medium business applications. Its networking solutions include communication processors, network processors, media processors, content-inspection processors, and physical layer devices, as well as software tools and segment specific applications, evaluation systems, and reference designs. The company also designs and sells enterprise networking devices for applications, such as Ethernet switches and routers. Its networking products are used in the wireless infrastructure, enterprise, and data center markets. The company sells its products to original equipment manufacturers in the server, storage, and networking industries, as well as through a network of resellers and distributors. LSI Corporation was founded in 1980 and is headquartered in San Jose, California.
Job Location : Bangalore Jobs
Experience: 0-1 yrs (Freshers Jobs)
Job Description
Des: ASIC DvDs Engineer 1
Job profile:
Participate in all the different phases of Physical design implementation of SoCs.
Participate in Block level Physical design of complex Chip/IPs.
Participate in STA and timing closure activities
Work with chip integration team closely in Timing closure
Complete the Block level/SoC Design including the physical design verification
Participate in chip level floor planning and hierarchical design
Required skills
Hands-on experience with back-end tools (floorplaning and place & route) preferably using ICC/Astro
Clock tree synthesis
Back-end design flows from Synthesis to physical design verification including various scan and BIST methodologies
Static timing analysis and timing closure
Physical design verification ( LVS, DRC)
Power analysis preferably with voltage storm/Cooltime
Chip finishing flow
As part of Design Implementation team, you will be responsible for all aspects of physical design implementation from Netlist to GDSII. Applicant will also be involved in chip floor planing, power analysis, full chip integration, timing closure, and physical verification (DRC/LVS/ERC/Antenna), tape out and mask review.
Applicant will also participate in establishing and defining implementation methodologies and flow automation. Experience should be focused on design implementation.
->Categorised under Software Engineer Jobs
Imagine your future. Accelerated.
Desired: M.Tech & B.E/ B.Tech from a reputed institute with good academic record specialization in EE, Computer Science Engineering
Experience: 0-1 years of experience and should have executed P & R for large chip designs
Experience in physical design of SoCs.
Candidate must have relevant experience
How to Apply:
Apply Here
Job Location : Bangalore Jobs
Experience: 0-1 yrs (Freshers Jobs)
Job Description
Des: ASIC DvDs Engineer 1
Job profile:
Participate in all the different phases of Physical design implementation of SoCs.
Participate in Block level Physical design of complex Chip/IPs.
Participate in STA and timing closure activities
Work with chip integration team closely in Timing closure
Complete the Block level/SoC Design including the physical design verification
Participate in chip level floor planning and hierarchical design
Required skills
Hands-on experience with back-end tools (floorplaning and place & route) preferably using ICC/Astro
Clock tree synthesis
Back-end design flows from Synthesis to physical design verification including various scan and BIST methodologies
Static timing analysis and timing closure
Physical design verification ( LVS, DRC)
Power analysis preferably with voltage storm/Cooltime
Chip finishing flow
As part of Design Implementation team, you will be responsible for all aspects of physical design implementation from Netlist to GDSII. Applicant will also be involved in chip floor planing, power analysis, full chip integration, timing closure, and physical verification (DRC/LVS/ERC/Antenna), tape out and mask review.
Applicant will also participate in establishing and defining implementation methodologies and flow automation. Experience should be focused on design implementation.
->Categorised under Software Engineer Jobs
Imagine your future. Accelerated.
Desired: M.Tech & B.E/ B.Tech from a reputed institute with good academic record specialization in EE, Computer Science Engineering
Experience: 0-1 years of experience and should have executed P & R for large chip designs
Experience in physical design of SoCs.
Candidate must have relevant experience
How to Apply:
Apply Here
